Samsung has announced the V10 BV-NAND storage chip, which is based on 10th generation vertical NAND architecture. The introduction of the chip took place at the Future of Memory and Storage 2026 (FMS) trade show held in the US.
The V10 BV-NAND is designed specifically for data centers rather than end-users. The technology aims to overcome performance bottlenecks in AI servers by combining high processing power with lower energy consumption.
Using a new wafer bonding technology, Samsung has achieved vertical stacking of over 400 layers. Samsung is the first manufacturer to implement this specific type of architecture in the semiconductor industry using this wafer bonding method.
Comparison of V10 BV-NAND to previous 9th generation NAND chips
Samsung disclosed that the areal density of its 10th Gen TLC V-NAND would be 28 Gb/mm2. Additionally, the 10th Gen TLC V-NAND can reach a maximum I/O speed of 5600 MT/s.
Next-generation memory technologies
In addition to BV-NAND, Samsung announced three next-generation memory technologies: zHBM, zNAND-O, and BV-NAND.
The zHBM architecture places HBM directly on top of an AI accelerator to reduce data travel distance. Samsung projects that zHBM will enable over 10x higher memory density, 3x better energy efficiency, and more than 50% lower thermal resistance than HBM5.
Samsung projects that zHBM can provide 8x the 'performance of HBM5'.
Some reports note that the '8x performance' claim is vague, as it does not specify if the figure refers to bandwidth or application performance.
The zNAND-O is a high-performance NAND memory currently in development. It enables placing four or eight stacks of NAND devices on top of logic dies. Samsung claims zNAND-O is suitable for edge AI systems running real-time, data-intensive inference workloads.
Samsung has not yet officially announced a commercial release date for the V10 BV-NAND chip. Both zHBM and zNAND-O technologies are years away from availability.
